![]() These solutions generally involve software-based enforcement of coherence with some hardware support. These factors raise cost concerns and present implementation challenges when trying to scale the hardware-based approach to larger and larger systems. the level of complexity, power consumption, and amount of silicon real estate required by coherence-enforcing hardware also increase.Hardware-based approaches provide a relatively fast and effective solution to the cache coherence problem.Multi-core systems typically employ hardware-based devices that enforce cache coherence and prevent cores from operating on invalid data.Without cache coherence, there is a possibility that invalid data will be provided from a cache to one of the cores. a core updates data within the memory block then previously cached versions of the memory block become invalid.multiple caches may store separate copies of the same memory block.the disclosure relates more specifically to computer-implemented techniques for ensuring the consistency of shared resource data in multi-core, multi-level, heterogeneous computer architectures that employ both hardware-managed and software-managed caches.the present disclosure relates generally, to cache coherence.G06F2212/10- Providing a specific technical effect. ![]() G06F2212/00- Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures.with bus monitoring or watching means in combination with broadcast means (e.g. G06F12/0833- Cache consistency protocols using a bus scheme, e.g.G06F12/0831- Cache consistency protocols using a bus scheme, e.g.G06F12/0837- Cache consistency protocols with software control, e.g.G06F12/0815- Cache consistency protocols.G06F12/0806- Multiuser, multiprocessor or multiprocessing cache systems.caches using pseudo-associative means, e.g. G06F12/0864- Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g.G06F12/0802- Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g.G06F12/08- Addressing or allocation Relocation in hierarchically structured memory systems, e.g.G06F12/02- Addressing or allocation Relocation.G06F12/00- Accessing, addressing or allocating within memory systems or architectures.G06- COMPUTING CALCULATING OR COUNTING.Assignors: AGARWAL, NIPUN, RAGHAVAN, Arun, BASANT, AARTI, DI BLAS, Andrea Publication of US20160328326A1 publication Critical patent/US20160328326A1/en Application granted granted Critical Publication of US10417128B2 publication Critical patent/US10417128B2/en Status Active legal-status Critical Current Adjusted expiration legal-status Critical Links Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by Oracle International Corp filed Critical Oracle International Corp Priority to US14/705,806 priority Critical patent/US10417128B2/en Assigned to ORACLE INTERNATIONAL CORPORATION reassignment ORACLE INTERNATIONAL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Original Assignee Oracle International Corp Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) ( en Inventor Andrea Di Blas Aarti BASANT Arun Raghavan Nipun Agarwal Current Assignee (The listed assignees may be inaccurate. ![]() ![]() Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Granted Application number US14/705,806 Other versions US10417128B2 Google Patents US20160328326A1 - Memory coherence in a multi-core, multi-level, heterogeneous computer architecture US20160328326A1 - Memory coherence in a multi-core, multi-level, heterogeneous computer architecture
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |